Publications
A. Singhal, Y. Machhiwar, S. Singh, G. Pahwa, and H. Agarwal, “ANN-based Framework for Modeling Process Induced Variation using BSIM-CMG Unified Model,” in Solid State Electronics, Elsevier, 2024 (Accepted).
A. Singhal, G. Gill, G. Pahwa, A. Lahgere, and H. Agarwal, “Improved Compact Modeling of Snapback Behaviour in ESD MOSFETs,” in IEEE SISPAD, California, USA, 2024 (Accepted).
A. Singhal, G. Pahwa and H. Agarwal, “A Novel Physics Aware ANN-Based Framework for BSIM-CMG Model Parameter Extraction,” in IEEE Transactions on Electron Devices, vol. 71, no. 5, pp. 3307-3314, May 2024, doi: 10.1109/TED.2024.3381917.
A. Singhal, P. Goyal and H. Agarwal, “Artificial Neural Network Driven Optimization for Analog Circuit Performance,” 2024 IEEE Latin American Electron Devices Conference (LAEDC), Guatemala City, Guatemala, 2024, pp. 1-4, doi: 10.1109/LAEDC61552.2024.10555739.
A. Singhal and H. Agarwal, “Physics Informed Neural Network Based Time-Independent Schrödinger Equation Solver,” 2024 8th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Bangalore, India, 2024, pp. 1-3, doi: 10.1109/EDTM58488.2024.10512058.
A. Singhal, G. Gill, G. Pahwa, C. Hu and H. Agarwal, “An Improved Robust Infinitely Differentiable Drift Resistance Model for BSIM High Voltage Compact Model,” 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Seoul, Korea, Republic of, 2023, pp. 1-3, doi: 10.1109/EDTM55494.2023.10103122.
A. Singhal, Y. Machhiwar and H. Agarwal, “Role of Negative Differential Resistance in Improving Analog Performance of Negative Capacitance FETs,” 2022 IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-6, doi: 10.1109/ICEE56203.2022.10117913.
G. Gill, A. Singhal, G. Pahwa, C. Hu and H. Agarwal, “Compact Modeling of Impact Ionization in High-Voltage Devices,” in IEEE Transactions on Electron Devices, vol. 70, no. 5, pp. 2389-2394, May 2023, doi: 10.1109/TED.2023.3253101.